1. Field of the Invention
Some conventional semiconductor memory devices use a sense amplifier consisting of a latch type differential amplifier circuit. The circuit arrangement of a conventional differential amplifier will be described below in terms of a sense amplifier section for amplifying the bit-line potential in a dynamic random access memory (DRAM) as an example.
2. Description of the Related Art
The sense amplifier section shown in FIG. 1 includes a bit line pair /BL less than 2 greater than  and BL less than 2 greater than  ( less than 2 greater than  is illustrated by example), an equalizer and multiplexer (EQLandMUX) 101, an N-channel sense amplifier (NSA) 102, an NSA common source line 103, an NSA set driver 104, and a DQ gate 105. The equalizer comprises N-channel transistors (hereinafter referred to as NFETs) Q11, Q12, and Q13. The multiplexer comprises NFETs Q14 and Q15. The NSA 102 comprises NFETs Q16 and Q17. The NSA common source line 103 provides a xe2x80x9c0xe2x80x9d write potential VBLL (e.g., Vss) to the common sources of the NFETs Q16 and Q17 in the NSA 102. The NSA set driver 104 provides VBLL to the NSA common source line 103. The DQ gate 105 comprises NFETs Q18 and Q19.
To the right of the DQ gate 105 are further provided a P-channel sense amplifier (PSA) 106, a PSA common source line 107, and a PSA set driver 108. The PSA 106 comprises P-channel transistors (hereinafter referred to as PFETs) Q20 and Q21. The PSA common source line 107 transfers a xe2x80x9c1xe2x80x9d write potential (e.g., VBLH) to the common sources of the transistors Q20 and Q21 in the PSA 106, and the PSA set driver 108 provides VBLH to the PSA common source line 107. Furthermore, the PSA 106 is followed by a multiplexer comprised of NFETs Q22 and Q23 and an equalizer comprised of NFETs Q24, Q25 and Q26.
Such a sense amplifier as described above is provided for each bit line pair; thus, as shown in the lower portion of FIG. 1, the same circuit is also provided for /BL less than 0 greater than  and BL less than 0 greater than  ( less than 0 greater than  is merely exemplary). The VBLH/2 power supply lines on the right and left supply the equalized potential VBLH/2 to the bit line pairs. CSL denotes a column select signal line. Though not shown, memory cells, each consisting of a cell capacitor and a cell transistor, are connected on the opposite sides of the sense amplifier section to each bit line pair.
The major part of the sense amplifier of FIG. 1 is formed from the NSA 102 and PSA 106 each of which has its transistors cross-coupled to the bit line pair. The common source line 103 of the NSA 102 is connected by the NSA set driver 104 consisting of an NFET to a bit line restore power supply line at the xe2x80x9c0xe2x80x9d write potential VBLL (e.g., Vss). The common source line 107 of the PSA 106 is connected by the PSA set driver 108 consisting of a PFET to a bit line restore power supply line at the xe2x80x9c1xe2x80x9d write potential VBLH.
With the conventional sense amplifier, as described above, the NSA set driver is formed of an NFET and the PSA set driver is formed of a PFET. At sense time, latch signals NSET and bPSET are set high and low, respectively, thereby amplifying a small potential difference between the bit lines to set the bit line BL (or the /BL) at xe2x80x9c1xe2x80x9d write potential on the high potential side and the bit line /BL (or the BL) at xe2x80x9c0xe2x80x9d write potential on the low potential side, respectively.
According to an aspect of the present invention there is provided a sense amplifier section of a semiconductor memory device that includes a memory cell array and a plurality of bit line pairs arranged in a column direction of the memory cell array. The sense amplifier section is configured to control the transfer of data to or from the memory cell array via the bit line pairs. The sense amplifier section includes an array of layout units respectively including circuit portions of sense amplifiers formed in a well region. None of the layout units include any contacts for biasing the well region. The sense amplifier also includes a contact disposed outside of the layout units and configured to bias the well region.
According to another aspect of the present invention there is provided a sense amplifier section of a semiconductor memory device that includes a memory cell array and a plurality of bit line pairs arranged in a column direction of the memory cell array. The sense amplifier section is configured to control the transfer of data to or from the memory cell array via the bit line pairs. The sense amplifier section includes an array of layout units respectively including circuit portions of sense amplifiers, wherein the layout units are disposed in the array of layout units at intervals smaller than intervals of the bit line pairs.
According to a further aspect of the present invention there is provided a sense amplifier section of a semiconductor memory device that includes a memory cell array and a plurality of bit line pairs arranged in a column direction of the memory cell array. The sense amplifier section is configured to control the transfer of data to or from the memory cell array via the bit line pairs. The sense amplifier section includes an array of sense amplifiers disposed at intervals smaller than intervals of the bit line pairs. The sense amplifier section also includes a varying region, in which the intervals of the sense amplifiers are obtained by changing the intervals of the bit line pairs formed in a portion in contact with a boundary between the sense amplifier section and the memory cell array.